1. Field of the Invention
The invention relates in general to a semiconductor circuit structure, and more particularly to a field device electrostatic discharge protective circuit.
2. Description of the Related Art
In the fabrication of an integrated circuit (IC), such as a dynamic random access memory (DRAM) or a static random access memory, electrostatic discharge (ESD) is one of the main factors causing IC damage. This is especially true for fabrication of a deep sub-micron IC. ESD is often seen in the work place. For example, when one walks on a carpet with semiconductor wafers, if relative humidity (RH) is high, an electrostatic voltage of about a few hundred volts may exist on one's body and wafers. If the RH is very high, the electrostatic voltage may be even as high as about a few thousand volts. If a conductive object occasionally contacts the wafers, a strong ESD could occur and damage the ICs on the wafers. ESD is an especially serious problem for fabrication of a complementary metal-oxide semiconductor (CMOS) device.
In order to protect wafers from ESD damage, many methods to resolve the ESD problem have been proposed. A conventional ESD protective circuit is incorporated between an internal circuit and a pad. FIG. 1 is a schematic, cross-sectional view showing a conventional field device ESD protective circuit. The conventional field device ESD protective circuit comprises an N-type field effect transistor (FET) 12, N-type metal oxide semiconductor (NMOS)16 and a buffer output device 18. The drain of the N-type FET 12 is electrically coupled to one side of a resistor 14. The gate of the N-type FET 12 is electrically coupled to an input port 10. The source of the N-type FET 12 is coupled to ground. The drain of the NMOS 16 is coupled to the other side of the resistor 14 and to the input terminal of the buffer input device 18. The gate and the source of the NMOS 16 are coupled to ground. The output terminal of the buffer input device 18 is coupled to an internal circuit 20.
Static charge or over-stress voltage from the input port 10 is discharged by the N-type FET 16 coupled to ground. On the other hand, the resistor 14 and the grounded NMOS 12 also can release over-stress voltage. The resistor 14 can inhibit an ESD current passing through the grounded gate of the NMOS 12. Thus, the internal circuit 20 is protected.
When the over-stress voltage is input from the input port 10, the N-type FET 12 becomes conductible due to a punch-through effect. A conductive rate of the punch-through effect is faster than a conductive rate of a junction breakdown, so that the punch-through effect can be used for protecting a device which has a low breakdown voltage. A threshold voltage of the N-type FET 12 is about 12-14V, so that current is more quickly conducted through the N-type FET. However, a breakdown voltage of a thin gate with a thickness of about 50 .ANG. is about 5-6V. If the internal circuit comprises the thin gate, the N-type FET 12 with the high threshold voltage cannot be used to protect the internal circuit.
Additionally, because the gate oxide layer becomes thinner as the integration of semiconductor devices is increased, the breakdown voltage of the gate oxide layer approaches or is lower than the junction voltage of the source/drain. Therefore, the protection from the ESD protective circuit becomes less effective. Moreover, the internal circuit design usually follows the minimum design rules, so the allowance spaces between the contact hole and the edge of the doped region and the between the contact hole and the edge of the gate electrode are too small to resist the huge electrostatic discharge transient current. Hence, devices are easily damaged by the FSD when the integration is high.